The Senior QA/DV Program Manager a highly skilled and driven Principal Technical Program Manager (TPM) to drive the execution, delivery, and quality assurance of multiple ASIC SOC hardware and BMC software solutions portfolios. In this role, you will lead the program management for our End-to-End Quality Assurance (QA) team, and drive the program execution for our complex SOC Design Verification projects (DV). You will have the opportunity to work closely with various engineering teams, from HW/SW design, verification, validation and system integration. Program Management & Execution Multi-Project Lifecycle Ownership: Track multiple parallel ASIC SOC projects from pre-silicon phases through to final deployment. Cross-Functional Alignment: Coordinate schedules and dependencies between QA, Software, Architecture, Design, and DV teams. Risk Mitigation & Resolution: Identify technical and schedule bottlenecks early to develop clear mitigation plans. Metrics & Reporting: Report key execution metrics and milestone readiness regularly to engineering leadership. QA Program Focus System-Level QA Strategy: Oversee the testing schedule for full server systems and BMC boards hosting the SOC. Bug Tracking & Resolution: Drive the end-to-end triaging, tracking, and closure of system-level defects with engineering teams. Hardware/Software Co-Verification: Manage program dependencies for QA teams validating firmware, security layers, and Linux OS. Automation & Infrastructure: Track the deployment of automated test regressions running on physical server infrastructure. DV Program Focus Milestone Tracking & Delivery: Drive schedule adherence for block-level, subsystem, and full-chip verification milestones. Bug Lifecycle Management: Monitor pre-silicon bug burn-down rates and prioritize critical fixes to keep tape-out schedules on track. Scope Tracking: Coordinate with DV team leads to ensure timelines account for coverage all critical components. Emulation & Pre-Silicon Planning: Drive reviews, schedule and track dependencies for emulation and FPGA development, and coordinate with design, DV and software teams.