Digital IC Design Engineer

<div class="content-intro"><p><strong>About Neuralink:</strong></p>

<p>We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.</p></div><p><strong>Team Description: </strong></p>

<p>The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. </p>

<p><strong>Job Description & Responsibilities: </strong></p>

<p>Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.</p>

<ul>

<li>Micro-architecture design and RTL implementation of: </li>

<ul>

<li>Low-power digital signal processors</li>

<li>Low-power general-purpose hardware accelerators</li>

<li>Low-power graphics processing units</li>

<li>Low-power radio MAC/PHY</li>

<li>Low-power serial link MAC/PHY</li>

</ul>

<li>Design and optimization of hardware/software interface with firmware engineers</li>

<li>Application-specific architecture optimization including:</li>

<ul>

<li>Complex system modeling for energy and performance benchmarks</li>

<li>Workload analysis and modeling</li>

<li>Energy/performance profiling and analysis</li>

<li>Leveraging architecture-level design trade-offs with process technology and workload type</li>

<li>Balancing cost and performance under manufacturing process variation </li>

</ul>

<li>Collaboration on silicon bring-up tests with verification engineers </li>

</ul>

<p><strong>Required Qualifications:</strong></p>

<ul>

<li>Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience</li>

<li>Evidence of exceptional ability in electrical engineering, computer science, or computer engineering</li>

<li>5+ years of experience in digital design</li>

<li>Expertise in SystemVerilog, C/C++, Python</li>

<li>Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools</li>

<li>Experience in designing digital signal processing pipelines, from algorithm to RTL</li>

</ul>

<p><strong>Preferred Qualifications:</strong><strong> </strong></p>

<ul>

<li>Experience in architecture optimization with process technology customization</li>

<li>Experience in the verification of complex digital systems, using industry standard tools</li>

<li>Experience in the physical design of complex digital systems, using industry standard tools</li>

<li>Experience testing and debugging digital system-on-a-chips</li>

<li>Functional modeling experience and logic verification with SystemVerilog, SystemC/C++</li>

<li>Experience automating tool flows</li>

<li>Experience with embedded design</li>

<li>Experience in processor instruction set architecture design</li>

<li>Experience in compiler back-end design and customization</li>

</ul><div class="content-pay-transparency"><div class="pay-input"><div class="description"><p><strong>Expected Compensation:</strong></p>

<p>The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.</p></div><div class="title">Base Salary Range:</div><div class="pay-range"><span>$116,000</span><span class="divider">—</span><span>$233,800 USD</span></div></div></div><div class="content-conclusion"><div>

<p><strong>What We Offer:</strong></p>

<p>Full-time employees are eligible for the following benefits listed below.</p>

<ul>

<li>An opportunity to change the world and work with some of the smartest and most talented experts from different fields</li>

<li>Growth potential; we rapidly advance team members who have an outsized impact</li>

<li>Excellent medical, dental, and vision insurance through a PPO plan</li>

<li>Paid holidays</li>

<li>Commuter benefits</li>

<li>Meals provided</li>

<li>Equity (RSUs) <em>*Temporary Employees & Interns excluded</em></li>

<li>401(k) plan <em>*Interns initially excluded until they work 1,000 hours</em></li>

<li>Parental leave <em>*Temporary Employees & Interns excluded</em></li>

<li>Flexible time off <em>*Temporary Employees & Interns excluded</em></li>

</ul>

</div></div>