<div class="content-intro"><p><strong>About Neuralink:</strong></p>
<p>We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.</p></div><p><strong>Job Description &amp; Responsibilities:&nbsp;</strong></p>
<p>We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.</p>
<p><strong>Required qualifications</strong>:</p>
<ul>
<li>Minimum 3 years of experience in digital ASIC verification.</li>
<li>Excellence in SystemVerilog.</li>
<li>Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell</li>
<li>Experience with code coverage and regression setup.</li>
<li>Bachelor's degree in a technical field OR equivalent experience.</li>
</ul>
<p><strong>Preferred qualifications</strong>:</p>
<ul>
<li>Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.</li>
<li>Experience on building test benches, testing, and debugging for a complex system-on-chip.</li>
<li>Experience in formal verification.</li>
<li>Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.</li>
<li>Experience with IEEE-1801 (UPF) based design simulation flows</li>
<li>Experience with low power gate level simulations</li>
<li>Exposure with low power formal verification flows</li>
<li>Strong hands-on experience in verification methodologies such as UVM</li>
<li>Knowledge of ARM/RISC-V processor, AMBA bus</li>
<li>Knowledge of power aware verification</li>
<li>Experience with FPGA/emulation</li>
<li>Experience with lab system bring up, writing diagnostic, and lab debugging</li>
</ul><div class="content-pay-transparency"><div class="pay-input"><div class="description"><p><strong>Expected Compensation:</strong></p>
<p>The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.</p></div><div class="title">Base Salary Range:</div><div class="pay-range"><span>$131,000</span><span class="divider">&mdash;</span><span>$243,000 USD</span></div></div></div><div class="content-conclusion"><div>
<p><strong>What We Offer:</strong></p>
<p>Full-time employees are eligible for the following benefits listed below.</p>
<ul>
<li>An opportunity to change the world and work with some of the smartest and most talented experts from different fields</li>
<li>Growth potential; we rapidly advance team members who have an outsized impact</li>
<li>Excellent medical, dental, and vision insurance through a PPO plan</li>
<li>Paid holidays</li>
<li>Commuter benefits</li>
<li>Meals provided</li>
<li>Equity (RSUs) <em>*Temporary Employees &amp; Interns excluded</em></li>
<li>401(k) plan <em>*Interns initially excluded until they work 1,000 hours</em></li>
<li>Parental leave <em>*Temporary Employees &amp; Interns excluded</em></li>
<li>Flexible time off <em>*Temporary Employees &amp; Interns excluded</em></li>
</ul>
</div></div>